Contact Us

Chasing the stars and seas, building a new era of aerospace together.

Business & Collaboration

Explore the stars together, achieve mutual success and a shared future.

Company Address

Kunxun Building, Haidian District, Beijing, China

Official Email

contact@spaceaigrid.com

Join Us

•Lead ground-based AI model training, iterative optimization, and lightweight adaptation for spaceborne deployment scenarios.
•Complete hardware adaptation, operator optimization, and inference acceleration to ensure efficient on-orbit model execution.
•Build, debug, and optimize the onboard AI inference platform; establish a standardized in-orbit inference runtime environment.
•Conduct in-orbit model performance testing, monitoring, and multi-dimensional metric evaluation; generate an evaluation report.
•Iteratively upgrade the model and optimize performance based on orbital operation data and field-verified issues.

•Bachelor's degree or above in Computer Science, Artificial Intelligence, Mathematics, Electrical Engineering, or related fields.
•3+ years of hands-on experience in deep learning algorithm development, 2+ years of project experience deploying models on edge devices. Experience with embedded AI development and CUDA performance tuning is a plus.
•Proficient in Python and C++ development, with expertise in CUDA programming. Capable of independently executing engineering tasks using TensorRT and Triton inference serving tools.
•Proficient in at least one mainstream deep learning framework (PyTorch or TensorFlow), with hands-on experience in ONNX model conversion and TensorRT deployment.
•Expert in core terminal-side acceleration technologies such as model quantization, sparsity optimization, and operator fusion. Proven track record of end-to-end project delivery—from solution design and implementation to performance validation.
•Experience in aerospace projects preferred.

•Lead hardware requirement decomposition, solution validation, schematic design, component selection, and project feasibility assessment.
•Complete the detailed design, simulation verification, and performance tuning of core hardware modules including heterogeneous compute units, high-speed interfaces, power systems, and storage systems.
•Collaborate with teams in collaborative logic development, embedded software, and structural design to conduct integrated system debugging. Accurately identify and resolve board-level and system-level hardware issues through closed-loop problem management.
•Create and iteratively maintain hardware lifecycle design documentation, including design specifications, BOMs, PCB layout constraints, and debug/test reports.
•Oversaw prototype development and debugging, leading initiatives to optimize signal integrity, electromagnetic compatibility, and environmental reliability.

•Bachelor's degree or above in Electronic Engineering, Communication, Microelectronics, Automation, or related fields
•3+ years of hardware R&D experience with a full lifecycle project background spanning solution design, prototyping, debugging, and delivery.
•Proficient in at least one mainstream hardware design tool, such as Cadence Allegro or Altium Designer.
•Strong foundation in analog and digital circuit theory, with hands-on experience in high-speed circuit design and SI/PI analysis and debugging.
•Proficient in FPGA, ARM, and heterogeneous SoC hardware design principles; skilled in high-speed interface protocols including DDR, PCIe, and Ethernet.
•Proficient with hardware test equipment such as oscilloscopes, spectrum analyzers, and logic analyzers; capable of independently locating, analyzing, and debugging hardware issues to completion.

•Background in R&D for aerospace satellite systems, military electronics, and high-reliability industrial equipment.
•Experience in hardware project development for Zynq heterogeneous platforms, embedded GPUs, and AI accelerators.

•Led the porting, feature pruning, and on-orbit lightweight adaptation of commercial 5G protocol stacks to meet low-power and high-reliability requirements for spaceborne equipment.
•Led full-module development and adaptation of the 5G Layer 2 stack, including ultra-long HARQ latency support, MAC-layer on-board scheduling optimization, RLC retransmission mechanism adaptation, and PDCP latency compensation with QoS optimization.
•Led end-to-end 5G L3 development and adaptation, implementing customized RRC signaling, NTN-specific IE field handling, cell selection/reselection rule adaptation, and on-board neighbor cell measurement strategy optimization.
•Optimize RRM wireless resource management algorithms; develop and iterate satellite high-mobility adaptation and inter-satellite/ground handover strategies.
•Complete NTN onboard random access enhancement, beam management adaptation, and multi-user concurrent access optimization. Perform targeted tuning of core performance metrics including throughput and BLER.

•Possess 3+ years of full-stack development and maintenance experience in 5G base station L2/L3 protocol stacks, with proficiency in core modules including MAC, RLC, PDCP, RRC, and RRM.
•Proficient in the core technical features of 3GPP R7/R8 NTN, with a deep understanding of low-Earth orbit (LEO) satellite challenges including high latency, large Doppler shifts, high-speed mobility, and wide-area coverage.
•Proficient in C; capable of independently porting protocol stacks, adapting to scenarios, troubleshooting issues, and optimizing algorithms.
•Capable of independently handling full-stack development for NTN protocols. Experience with lightweight, high-reliability requirements for spaceborne communication equipment is a plus. Proficiency in using AI tools to assist coding and improve testing efficiency is preferred.

Jobs are being updated continuously